1. Field of the Invention
The present invention relates to a semiconductor memory device having a multibank configuration.
2. Description of the Related Art
In a large capacity memory such as a 64M or 256M DRAM, it is a widespread practice to adopt a method in which a plurality of independently operating memory banks are provided within a chip to be interleaved among these banks.
For instance, in the case of a memory with a wide internal bus width such as a 64M DRAM having four banks of 16M each, the configuration of the banks is such that, they are arranged in a line with the short side of each bank placed along the short side of the chip, and I/O bus lines are shared among the banks, for the purpose of improving the integration level. In particular, in a high speed DRAM with the operating frequency ranging from 800 MHz to 1 GHz, it is necessary to provide the I/O pads at a chip edge because of the conspicuous deterioration in the transmission characteristics due to inductance of several nH existing in the lead frame. Accordingly, it is necessary to arrange the pads, external I/O circuits, and an edge of the chip.
Referring to FIG. 1, a conventional semiconductor memory device with multibank configuration will be described. This conventional semiconductor memory device is provided with bank-A 1, bank-B 2, bank-C 3, and bank-D 4 arranged in the direction of the short side of each bank, complementary I/O buses T0 and N0 shared by the bank-A 1 to bank-D 4, a data amplifier part 105 which reads data on the I/O buses T0 and N0 and outputs the read data to a data bus RDL0, and an output buffer 6 which outputs the output data in response to the supply of read data from the data bus RDL0.
The data amplifier part 105 is provided with an I/O bus data amplifier connection part 151 which is the connection section with the I/O buses TO and NO, and carries out the reading of various banks.
The I/O buses T0 and N0 are connected respectively to bit lines D0 and DB0 which are complementary with each other on the bank-A 1, bit lines D1 and DB1 complementary on the bank-B 2, bit lines D2 and DB2 complementary on the bank-C 3, and bit lines D3 and DB3 complementary on the bank-D 4.
Referring to FIG. 2 showing a detailed circuit diagram of an I/O bus and bit line connection part T1 which is the connection section of the I/O buses T0 and N0 with the bit lines D0 and DB0, this I/O bus bit line connection part T1 is provided with NMOS transistors N60 and N61 whose respective drains are connected to I/O buses T0 and N0, respectively, whose respective sources are connected to the bit lines D0 and DB0, respectively, and whose respective gates are connected in common and is connected to a column selection signal line C0. In addition, though not shown, the bit lines D0 and DB0 are connected to memory cells and to sense amplifiers for amplifying the data in the memory cells.
Similarly, an I/O bus bit line connection part T2 is connected to the I/O buses T0 and N0 and the bit lines D1 and DB1, an I/O bus bit line connection part T3 is connected to the I/O buses T0 and N0 and the bit lines D2 and DB2, and an I/O bus bit line connection part T4 is connected to the I/O buses T0 and N0 and the bit lines D3 and DB3.
Referring to FIG. 3 showing a detailed circuit diagram of the data amplifier part 105 and the I/O bus data amplifier connection part 151, the I/O bus data amplifier connection part 151 is provided with PMOS transistors P70 and P71 whose respective sources are connected to the I/O buses T0 and N0, respectively, whose respective drains are connected to nodes S0 and S1, respectively, of the data amplifier part 105, and whose respective gates are connected in common and is connected to an I/O bus selection signal RSW.
The data amplifier part 105 is a latch type data amplifier part in which data are read by latch action. It is provided with PMOS transistors P51 and P52 whose respective sources are connected to a power supply VD and whose respective gates are mutually connected to the drains of the opposite transistors, NMOS transistors N51 and N52 whose respective drains are connected to the drains of the transistors P51 and P52, respectively, to form complementary output nodes S0 and S1, whose respective gates are connected to the gates of the transistors P51 and P52, respectively, and whose respective sources are connected in common, an NMOS transistor N53 whose drain is connected to the common connection point of the transistors N51 and N52, whose source is connected to the ground, and whose gate is connected to a data amplifier activation signal DAE, and a buffer BUF0 which is connected to the node S0 and outputs an output signal after buffering it to the data bus RDL0.
Next, the read operation of the conventional semiconductor memory device will be described. First, assume that an H level and L level read data are generated on the bit lines D0 and DB0, respectively. The NMOS transistors N60 and N61 are energized in response to the transition of the column selection signal line C0 to the H level, and corresponding to the read data, transfer H and L level potentials to the I/O buses T0 and N0, respectively. As a result, the potential of the I/O bus N0 becomes lower compared with the potential of the I/O bus T0, and a potential difference of, for example, 300 mV is generated between the I/O buses T0 and N0. This potential difference is transmitted to the nodes S0 and S1 of the data amplifier part 105 by bringing the I/O bus selection signal RSW to the L level, and bringing the transistors P70 and P71 of the I/O bus data amplifier connection part 151 to the energized state. In this state, the nodes S0 and S1 are brought to H and L levels, respectively, by bringing a data amplifier activation signal DAE to the H level and energizing the transistor N53 to amplify the potential difference. In this way, the buffer amplifier BUF0 outputs the H level of the node S0 to the data bus RDL0 to transmit the H level to the data bus RSL0. The data on the data bus RDL0 is output to the outside by the output buffer 6.
The read operation for the other banks, namely, bank-B to bank-D, is similar to the above, and the data on the bit lines connected to respective banks are output to the outside.
The conventional memory device described above has a configuration in which the short sides of a plurality of banks are arranged in a line along the direction of the short side of the chip, and the I/O bus lines are shared by these banks. Accordingly, the length of the I/O bus lines is almost equal to the length of the short side of the chip, so that the load-carrying capacitance per I/O bus line is very high. Therefore, when the banks A and B, which are arranged on the other side of, and are situated physically away from, the data amplifier part, are to be accessed, the data transfer from the bit lines to the I/O bus lines takes a long time, which leads to a drawback that it is a factor in the deterioration of the read access speed.